1. Field of the Invention
The present invention relates to a voltage/current conversion circuit.
2. Description of Related Art
Reference is now made to FIG. 5 which illustrates the configuration of a sampling-type voltage/current conversion circuit 1 disclosed in “A 35 MS/s and 2V/2.5V Current-mode Sample-and-Hold Circuit with an Input Current Linearization Technique”, Asian solid-state circuits conference, 2005 (IEEE), Paper No. P2-20, pp. 445 to 448, as an example of conventional voltage/current conversion circuits. As shown in FIG. 5, the voltage/current conversion circuit 1 includes resistors R11 and R21, current sampling circuits 11 and 21, current mirror circuits 12 and 22, and a sampling error correction circuit 30. Input terminals IN1 and IN2 of the voltage/current conversion circuit 1 are each connected to an input signal source to receive an input signal Vin. It is assumed herein that a voltage input to the input terminal IN1 is denoted by Vin1 and a voltage input to the input terminal IN2 is denoted by Vin2.
The resistor R11 is connected between the input terminal IN1 and the current sampling circuit 11. The resistor R21 is connected between the input terminal IN2 and the current sampling circuit 21. Each of the resistors R11 and R12 has a function of converting an input voltage into a current in the voltage/current conversion circuit 1.
The current sampling circuit 11 includes transistors M11 to M13, an amplifier G11, a sampling capacitor C11, a switch SW11, and a constant current source CC11. The current sampling circuit 21 includes transistors M21 to M23, an amplifier G21, a sampling capacitor C21, a switch SW21, and a constant current source CC21.
The current mirror circuit 12 includes transistors M14 and M15, an amplifier G12, and constant current sources CC12 and CC13. The current mirror circuit 22 includes transistors M24 and M25, an amplifier G22, and constant current sources CC22 and CC23. The drains of the transistors M15 and M25 are connected to output terminals OUT1 and OUT2, respectively.
To achieve pseudo differential operation, the current sampling circuits 11 and 21 have the same configuration, and the current mirror circuits 12 and 22 have the same configuration.
The sampling error correction circuit 30 includes transistors M31 and M32, and a constant current source CC31. Note that the constant current sources CC11 to CC31 are bias-use constant current sources.
The operation of the above-mentioned voltage/current conversion circuit 1 will be briefly described. Since the current sampling circuits 11 and 21 have the same configuration and the current mirror circuits 12 and 22 have the same configuration, only the operation of each of the current sampling circuit 11 and the current mirror circuit 12 is herein described.
First, the input impedance of the current sampling circuit 11 is lowered, because the amplifier G11 has a large gain. Further, the finite input impedance of the current sampling circuit 11 is corrected by the sampling error correction circuit 30. Thus, the potential at a node A1 is adjusted by the amplifier G11, the transistor M11, and the sampling error correction circuit 30 so as to be held constant at a ground potential GND irrespective of the input voltage Vin1. Accordingly, a current input to the current sampling circuit 11 has a value obtained by dividing substantially ideally the input voltage Vin1 by the resistor R11.
The switch SW11 receives a clock signal CLK as shown in FIG. 6. The switch SW11 is driven by the clock signal CLK. The switch SW11 is turned on when the clock signal CLK is at high level as shown in a time period S1 between a time t1 and a time t2, for example, and the current sampling circuit 11 enters a sampling mode. Further, as shown in a time period H1 between the time t2 and a time t3, the switch SW11 is turned off when the clock signal CLK is at low level, and the current sampling circuit 11 enters a hold mode.
In the sampling mode (when the switch SW11 is in the ON state), a node B1 is connected to each of the sampling capacitor C11 and the gates of the transistors M12 and M13. As a result, the gate-source voltage of each of the transistors M11 to M13 is held as the charging voltage of the sampling capacitor C11. The voltage/current conversion circuit 1 outputs a current, which is sampled by the gate-source voltage of the transistor M12 obtained at this time, i.e., the voltage at the node B1, as an output current Iout1 from the output terminal OUT1 via the next-stage current mirror circuit 12.
In the hold mode (when the switch SW11 is in the OFF state), the node B1 is disconnected from the sampling capacitor C11 and from the gates of the transistors M12 and M13. As a result, the transistors M12 and M13 are driven by the hold voltage of the sampling capacitor C11 at the time of switching from the sampling mode to the hold mode. Accordingly, the voltage/current conversion circuit 1 outputs a current, which is sampled by the hold voltage of the sampling capacitor C11 obtained at this time, as the output current Iout1 from the output terminal OUT1 via the next-stage current mirror circuit 12. Meanwhile, an output current Iout2 is output from the output terminal OUT2. The output currents Iout1 and Iout2 are in a differential relationship, and are output as differential signals from the output terminals OUT1 and OUT2.
The drains of the transistors M13 and M23 are connected to the output terminals OUT2 and OUT1, respectively, so as to cancel the charge injection effect from the switches SW11 and SW21.